As the dimensions of metal oxide semiconductor (MOS) transistors continue to shrink materials other than silicon oxide are currently being used to form the transistor gate dielectric layer. For MOS transistors with a gate length of less than 30 nm it is estimated that a silicon oxide thickness of 10–15 angstroms will be required to form the gate dielectric layer. One important limitation in determining the suitability of various materials for use in forming the gate dielectric is the amount of gate leakage current that results. In general the gate leakage current increases as the thickness of the gate dielectric layer decreases. One method for increasing the actual gate dielectric layer thickness without affecting transistor performance is to use materials that possess a higher dielectric constant (i.e., high K dielectric) compared to silicon oxide. It is estimated that for low power transistors that need silicon oxide dielectric layers of less that 15 Angstroms a high K dielectric will be necessary. In addition for high performance devices with a required silicon oxide dielectric layer thickness of 10 Angstroms a high K dielectric will also be required. (see International Technology Roadmap for Semiconductors (SIA, San Jose, Calif.) http//public.itrs.net, 2001) Some of the high K dielectrics current being investigated are HfO2, ZrO2, Al2O3, silicates, aluminates, HfSiON, HfAlON, and HfON.
MOS transistors formed using high K dielectric layers and polysilicon gate electrodes have exhibited large threshold voltage shifts. The threshold voltage shifts are especially large for PMOS transistors that typically have polysilicon gate electrodes that have been doped p-type. For CMOS integrated circuits to function correctly the threshold voltages of the NMOS and PMOS transistors have to be carefully controlled to be less than the supply voltage. The threshold voltage shifts exhibited using high K dielectric and polysilicon gate electrodes will cause CMOS integrated circuits comprising transistors with these layers to be inoperable. In addition to threshold voltage shifts for high K dielectrics, boron penetration and polysilicon depletion effects are also problems that affect PMOS transistors as the thickness of the dielectric layer is reduced. The method of the instant invention provides a solution to the above-described problems of threshold voltage shift, boron penetration, and polysilicon depletion.